nand2mario spent a month adding features to z486, his 486-class FPGA CPU core, and then went looking for the moment PC gaming changed — the arrival of 3D accelerators. The card that did it for him was the 3dfx Voodoo, seen through Need for Speed II SE. Could it be recreated in programmable logic now that the CPU existed?

The result is zSST, a SystemVerilog implementation of Voodoo Graphics (SST-1), combined with z486 into z486 XL: a DOS PC with Voodoo graphics running inside a Xilinx KV260. Tomb Raider runs with its original Glide renderer.

The Voodoo’s design constraints are worth resurfacing:

  • Five command registers, one drawing primitive: a prepared triangle.
  • No hardware transform-and-lighting. The host CPU did transform, vertex lighting, clipping, and projection; SST-1 only turned screen-space triangles into pixels.
  • Two ASICs did the rest — the FBI (framebuffer interface) and the TMU (texture mapping unit).
  • “One pixel per clock” was a throughput claim, not a latency claim: different pixels occupied different pipeline stages at once.
  • Software could submit IEEE floats, but the machinery ran on fixed point — X/Y in 12.4, RGBA in 12.12, Z in 20.12, S/W and T/W in 14.18.
  • Bilinear filtering cost four texel reads per filtered sample.

The pipeline turned out to be the easy half. The original card kept it fed with dedicated 64-bit paths to four-way interleaved EDO RAM, assigning a bank to each even/odd row × column combination so that any 2×2 texel window lands one texel in each bank. The KV260 has no such luxury: renderer, CPU, and scanout share DDR through separate AXI ports, and bandwidth alone is useless there. A 128-bit port at 100 MHz is theoretically 1.6 GB/s, but a 64-byte read measured 189 MiB/s against 1,370 MiB/s for a 4 KiB read, with first data arriving after roughly 28 clocks.

zSST answers with the CPU playbook instead — an 8 KiB texture cache, eight outstanding line fetches, a replay queue that parks samples waiting on memory while cached samples proceed, and a 64-entry reorder buffer to restore original ordering before results move downstream. The framebuffer side adds separate colour and depth/alpha caches, write combining into 128-bit requests, forwarding of not-yet-written values, and in-order retirement.

The numbers are reported honestly: 78.5 MPix/s textured and 72.8 MPix/s with depth test and blending at 100 MHz in simulation, against published Voodoo 1 figures of 43 and 37 MPix/s at 50 MHz — a comparison the author labels explicitly as not apples-to-apples. On real hardware Tomb Raider produced about 12 buffer swaps per second, CPU-bound. For non-Voodoo games the machine runs max-detail Doom at 38.5 FPS and Quake at 8.1 FPS.

What stands out is that the bottleneck moved while the problem didn’t. In 1996 the answer was silicon: dedicated buses, conflict-free interleaving, all four bilinear texels arriving together. In 2026 the answer is latency tolerance: caches, concurrency, and out-of-order completion. Same requirement, opposite mechanism — and a reminder that the unglamorous memory subsystem, not the vertex math, is where the engineering actually sits.